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Completion Detection in Asynchronous Circuits
Toward Solution of Clock-Related Design Challenges
Intended Audience
This book is intended for designers with experience in traditional (clocked) circuit design, seeking information about asynchronous circuit design, in order to determine if it would be advantageous to adopt asynchronous methodologies in their next design project.
Approach and Validation
The author introduces a generic approach for implementing a deterministic completion detection scheme for asynchronous bundled data circuits that incorporates a data-dependent computational process, taking advantage of the average-case delay. The author validates the architecture using a barrel shifter, as shifting is the basic operation required by all the processors.
Purpose and Benefits
The generic architecture proposed in this book for a deterministic completion detection scheme for bundled data circuits will facilitate researchers in considering the asynchronous design style for developing digital circuits.
