Automatic Analog IC Sizing and Optimization Constrained with PVT Corners and Layout Effects

£89.50

Automatic Analog IC Sizing and Optimization Constrained with PVT Corners and Layout Effects

Electronics engineering Electronics: circuits and components Computer architecture and logic design

Authors: Nuno Lourenco, Ricardo Martins, Nuno Horta

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Collection: Engineering

Language: English

Published by: Springer

Published on: 29th July 2016

Format: LCP-protected ePub

Size: 5 Mb

ISBN: 9783319420370


Introduction

This book introduces readers to a variety of tools for automatic analog integrated circuit (IC) sizing and optimization. The authors provide a historical perspective on the early methods proposed to tackle automatic analog circuit sizing, with emphasis on the methodologies to size and optimize the circuit, and on the methodologies to estimate the circuit’s performance.

Design and Optimization

The discussion also includes robust circuit design and optimization and the most recent advances in layout-aware analog sizing approaches. The authors describe a methodology for an automatic flow for analog IC design, including details of the inputs and interfaces, multi-objective optimization techniques, and the enhancements made in the base implementation by using machine learning techniques.

Gradient Model and Layout Effects

The Gradient model is discussed in detail, along with the methods to include layout effects in the circuit sizing. The concepts and algorithms of all the modules are thoroughly described, enabling readers to reproduce the methodologies, improve the quality of their designs, or use them as starting point for a new tool.

Application Examples

An extensive set of application examples is included to demonstrate the capabilities and features of the methodologies described.

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